Managing BGA test socket SI characterization

• Published in: 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013) pp. 589 - 591
• Main Authors: Lin Chee-Hoe, Ng Hui-Ying, Wong Wui-Weng
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2013
• Subjects: Couplings; Impedance; Pins; Silicon; Sockets; Transmission line matrix methods; Transmission line measurements
• DOI: 10.1109/EPTC.2013.6745788

In the area of high speed BGA products, such as APUs and GPUs, new revision of NPI (New Product Introduction) comes rapidly, and frequently involves change in package footprint. Test socket for the BGA package has to be characterized every time it involves a socket pin design change. This paper introduces an effective Signal Integrity (SI) characterization method for BGA test sockets used in high speed system level testing platforms. This method is referred as Coupling Pin Extraction Method (CPEM), in this paper. Loop Inductance (Lloop) and Coupling Capacitance (Ccouple) of socket pins under test are critical electromagnetic parameters which can be extracted using the proposed CPEM. CPEM is carefully crafted such that the Lloop and Ccouple can be consistently extracted using both measurement and simulation, with a single package footprint. Well-established 2-port VNA measurement is used in CPEM measurement of the targeted pin to the surrounding pins in a well defined Signal and Ground pin patterns. Similarly, Quasi-static Electromagnetic (Q-EM) simulation can be used to extract that Lloop and Ccouple as mentioned in the above. The extracted Lloop and Ccouple can then be used to derive Characteristic Impedance (Zo), Propagation Delay (Tdelay) and Coupling Coefficient (Kc). These derived parameters are more robust and better to address the SI performance of a high speed BGA socket.