Fault tolerant SRAM by redundant array structure

Detection and corrective measures of faults in Static Random Access Memory (SRAM) is always been thrust area of research. These faults occur due to physical failure, device parameter variations and process variations. For smooth operation of the circuit, device should be made fault tolerant. Some of...

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Bibliographic Details
Published in2015 International Conference on Pervasive Computing (ICPC) pp. 1 - 4
Main Authors Tak, Sheetal, Mali, Madan
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2015
Subjects
Algorithm design and analysis
Arrays
Built-In Redundancy Analysis (BIRA)
Built-In Self Test (BIST)
Circuit faults
embedded memory
Layout
Maintenance engineering
Random access memory
Redundancy
repair rate
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Summary:Detection and corrective measures of faults in Static Random Access Memory (SRAM) is always been thrust area of research. These faults occur due to physical failure, device parameter variations and process variations. For smooth operation of the circuit, device should be made fault tolerant. Some of the faults which cannot be repaired, reconfiguration has to be made to bypass such fault. Addition of redundant column in SRAM structure so as to make it fault tolerant is proposed in this paper. An array of 256X8 (2Kb) is designed; layout is done and simulated along with the redundant column of 256X1. The redundancy is 12.5% for the designed array.
DOI:10.1109/PERVASIVE.2015.7087128