Low noise resistive analog front-end with automatic offset calibration loop

This paper presents a low noise resistive analog front-end (AFE) with automatic offset calibration loop. The capacitive transimpedance amplifier (CTIA) with correlated double sampling (CDS) technique is adopted to achieve low noise characteristics. The AFE employs automatic offset calibration loop (...

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Bibliographic Details
Published in2015 International SoC Design Conference (ISOCC) pp. 231 - 232
Main Authors Hyungseup Kim, Haryong Song, Yunjong Park, Hyoungho Ko
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2015
Subjects
analog front-end (AFE)
automatic offset calibration loop (AOCL)
Calibration
Capacitors
correlated double sampling (CDS)
Electronics packaging
Integrated circuits
Layout
Resistance
resitive AFE
Sensors
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Summary:This paper presents a low noise resistive analog front-end (AFE) with automatic offset calibration loop. The capacitive transimpedance amplifier (CTIA) with correlated double sampling (CDS) technique is adopted to achieve low noise characteristics. The AFE employs automatic offset calibration loop (AOCL) to reduce the offset variations due to the fabrication imperfections. The automatic offset calibration loop is implemented using successive approximation register (SAR) logic and binary-weighted current-mode digital-to-analog converter (DAC). The analog output tracks the reference voltage using the binary search algorithms. The AFE is fabricated in 0.18μm 1P6M CMOS process. The core chip size of the AFE without I/O p-ad s is 1.76 mm 2 .
DOI:10.1109/ISOCC.2015.7401732