An Efficient Low Power Full Adder Architecture Using Memristor

• Published in: 2023 4th International Conference on Smart Electronics and Communication (ICOSEC) pp. 270 - 276
• Main Authors: R, Senthamizh Selvi, Nair, Resmi R, I, Sooraj, S., Subhishvar
• Format: Conference Proceeding
• Language: English
• Published: IEEE 20.09.2023
• Subjects: 2:1MUX; Energy efficiency; Full Adder; Logic gates; Memristor; Memristors; MOSFET; Power Consumption; Power demand; Threshold voltage; Throughput
• DOI: 10.1109/ICOSEC58147.2023.10276217

The problem addressed in the efficient low-power full adder architecture using memristors is to design a full adder circuit that minimizes power consumption while maintaining high performance and reliability. Traditional CMOS-based full adders can be power-hungry, especially in large-scale arithmetic circuits, limiting their use in low-power applications. The challenge is to exploit the unique properties of memristor devices to create an energy-efficient and high-performance full adder architecture. In this paper logic gates such as AND, OR, XNOR gates are designed using Memristor Ratioed Logic and by using the logic circuits combinational circuits such 2:1MUX is designed and furthermore, a low power area efficient full adder circuit is designed. The designed circuit is simulated in LTspice which has 11 NMOS transistors and 13 memristors and found that it provides 98% improvement in power consumption than the traditional CMOS full adder which has 28 transistors. The innovation lies in the use of memristor technology to design a low-power full adder architecture. The integration of memristors with traditional CMOS logic allows for novel design approaches that reduce power consumption while maintaining high-speed performance. The adaptive memristors adapt to varying input patterns, leading to dynamic optimization of the circuit's resistance states for improved energy efficiency. The parallelism and pipelining techniques effectively exploit the unique properties of memristors to achieve high throughput and reduced latency. Previous work on low-power full adder architectures has predominantly focused on CMOS-based designs, where power reduction techniques involve voltage scaling, threshold voltage adjustment, and gate sizing. In contrast, the proposed architecture stands out by incorporating memristors to achieve power savings beyond what traditional CMOS circuits can offer. The non-volatile memory capability of memristors enables power-efficient state retention during power interruptions, enhancing overall system reliability. Comparing the results with the most recent related work, the proposed memristor-based full adder demonstrates superior power efficiency and reduced delay. The adaptive memristors and parallel processing techniques significantly reduce power consumption, while pipelining reduces the overall latency. The circuit's performance is validated through rigorous simulation and testing, showcasing its effectiveness in low-power applications and making it a competitive choice compared to the most recent power-efficient full adder designs.