Design of a Comparator with Improved Noise, Delay Time and PSRR for a Single-Slope ADC

• Published in: 2024 International Conference on Electronics, Information, and Communication (ICEIC) pp. 1 - 4
• Main Authors: Jang, Heon-Bin, Kim, Yeong-Seok, Cheon, Jimin
• Format: Conference Proceeding
• Language: English
• Published: IEEE 28.01.2024
• Subjects: Capacitors; CIS (CMOS Image Sensor); CMOS image sensors; CMOS process; comparator; Layout; miller capacitor; Power supplies; PSRR (Power Supply Rejection Ratio); Simulation; single-slope ADC; split-length transistor; Voltage
• ISSN: 2767-7699
• DOI: 10.1109/ICEIC61013.2024.10457274

In this paper, we propose a comparator structure with improved noise, delay time, and power supply rejection ratio (PSRR) of a single-slope ADC used in CMOS image sensor (CIS). To improve the noise characteristics, a capacitor is inserted to reduce the bandwidth. However, the delay time and PSRR characteristics are worse. The proposed comparator uses a spilt-length transistor at the input of the comparator to improve the PSRR, and the PSRR is improved by isolating the capacitor from the power supply voltage and ground. Simulation results show that the proposed structure has improved PSRR and noise compared to the existing structures, and the delay time and layout area of the comparator are improved due to the smaller size of the capacitor. The proposed comparator is designed using a 0.18-μm CMOS process.