A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology

A high speed IRIW two port 32Kbit (128×256) SRAM with single port 6T bitcell macro is proposed. A Read-Then-Write (RTW) double pump CLK generation circuit with TRKBL bypassing is proposed to enhance read performance. Double metal scheme is applied to improve signal integrity and overall operating cy...

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Bibliographic Details
Published in2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
Main Authors Zhang, Nick, Kim, Young Suk, Hsu, Peter, Kim, Samsoo, Tao, Derek, Liao, Hung-Jen, Wang, P.W., Yeap, Geoffrey, Li, Quincy, Chang, Tsung-Yung Jonathan
Format Conference Proceeding
LanguageEnglish
Published JSAP 11.06.2023
Subjects
1R1W
5nm
double pump
FinFETs
High performance computing
Metals
Random access memory
Semiconductor device measurement
Silicon
SRAM
Very large scale integration
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Summary:A high speed IRIW two port 32Kbit (128×256) SRAM with single port 6T bitcell macro is proposed. A Read-Then-Write (RTW) double pump CLK generation circuit with TRKBL bypassing is proposed to enhance read performance. Double metal scheme is applied to improve signal integrity and overall operating cycle time. A Local Interlock Circuit (LIC) is introduced in Sense-Amp to reduce active power and push Fmax further. The silicon results show that the slow corner wafer was able to achieve 4. 24GHz at 1.0V/100°C in 5nm FinFET technology.
ISSN:2158-9682
DOI:10.23919/VLSITechnologyandCir57934.2023.10185268