Review of Hardware Implementations of Convolution for Discrete Wavelet Transform

Field programmable gate arrays (FPGAs) have often been used as hardware accelerators for digital signal processing (DSP) algorithms such as convolution and filtering operations. This work is a review of hardware implementations of the convolution operation specific to the discrete wavelet transform...

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Bibliographic Details
Published in2022 IEEE North Karnataka Subsection Flagship International Conference (NKCon) pp. 1 - 4
Main Authors C, Ramprakash, Prasad, Skanda, R, Pratyusha, Jayaramu, Raghu
Format Conference Proceeding
LanguageEnglish
Published IEEE 20.11.2022
Subjects
acceleration
Computer architecture
Convolution
Digital signal processing
Discrete wavelet transforms
distributed arithmetic
FPGA
Logic gates
residue number system
Signal processing algorithms
Transforms
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Summary:Field programmable gate arrays (FPGAs) have often been used as hardware accelerators for digital signal processing (DSP) algorithms such as convolution and filtering operations. This work is a review of hardware implementations of the convolution operation specific to the discrete wavelet transform (DWT). For such applications, read-only memory (ROM)-based architectures are known for their speed and performance. Two such architectures-distributed arithmetic (DA) and residue number system (RNS) are reviewed. Hardware utilization of both architectures using similar inputs and parameters on the Digilent Nexys-A7-100T field programmable gate array (FPGA) platform using Xilinx Vivado and other open-source tools are reported. Distributed arithmetic (DA) is found to be favourable for small input lengths, but residue number system (RNS) will surpass it for larger input lengths. A parallel distributed arithmetic (DA) implementation is also implemented, that offers significant computational speed-up at minimal power cost.
DOI:10.1109/NKCon56289.2022.10126593