Impacts of Clock Constraints on Side-Channel Leakage of HLS-designed AES Circuits

Many IoT devices such as FPGAs are at risk of side-channel attacks. To ensure security, cryptographic circuits such as AES must be implemented on FPGAs. In recent years, technologies to automatically generate RTL circuits from high-level languages such as C/C++ have become popular. In this paper, we...

Full description

Saved in:
Bibliographic Details
Published in2023 International Conference on Electronics, Information, and Communication (ICEIC) pp. 1 - 2
Main Authors Miura, Yuto, Mizuno, Takumi, Nishikawa, Hiroki, Kong, Xiangbo, Tomiyama, Hiroyuki
Format Conference Proceeding
LanguageEnglish
Published IEEE 05.02.2023
Subjects
AES
Clock constraints
Correlation
Energy consumption
high-level synthesis
Internet of Things
Measurement
Resistance
Security
side-channel attack
Side-channel attacks
T-test
Online AccessGet full text

Cover

More Information
Summary:Many IoT devices such as FPGAs are at risk of side-channel attacks. To ensure security, cryptographic circuits such as AES must be implemented on FPGAs. In recent years, technologies to automatically generate RTL circuits from high-level languages such as C/C++ have become popular. In this paper, we design seven AES circuits by high-level synthesis and investigate the relationship between clock constraints and security. T-tests are used to evaluate the security from four metrics. Since the correlation varies depending on the metrics, the circuit design is realized by considering not only security but also circuit performance.
ISSN:2767-7699
DOI:10.1109/ICEIC57457.2023.10049959