Implementation of Routing-denser PnR Flow for an Efficient IC Block Level Design

This paper presents Place and Route (PnR) flow for a block level design by setting a target for routing density. The PnR flow includes the placement of standard cells and routing of interconnects between them. Routing density is a key factor in determining the performance and reliability of the desi...

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Bibliographic Details
Published in2023 Second International Conference on Trends in Electrical, Electronics, and Computer Engineering (TEECCON) pp. 293 - 297
Main Authors C, Jenila, Kumar, Kummari Sudheer, S, Chenna Keshava Reddy, Sreekanth, Talakayala, Rao, Thota Venkata Durga
Format Conference Proceeding
LanguageEnglish
Published IEEE 23.08.2023
Subjects
Clock Tree Synthesis
Design for manufacturing (DFM)
Design Rule Checking(DRC)
Graphic Design System
Graphical User Interface
Integrated circuit interconnections
Layout versus synthetic (LVS)
Manufacturing
Power and Ground
Quality of Results
Register-transfer level
Reliability engineering
Routing
Wires
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Summary:This paper presents Place and Route (PnR) flow for a block level design by setting a target for routing density. The PnR flow includes the placement of standard cells and routing of interconnects between them. Routing density is a key factor in determining the performance and reliability of the design, as it affects the signal propagation and timing constraints. In this project, a target routing density will be set based on the design requirements, and the PnR flow will be optimized to achieve this density while meeting the design constraints. The flow will be implemented using industry-standard EDA tools and validated on a testbench to ensure its functionality and performance. The proposed flow can be used as a basis for designing complex digital circuits and systems with high-performance requirements.
DOI:10.1109/TEECCON59234.2023.10335847