A FPGA-Based Iterative 6DoF Pose Refinement Processing Unit for Fast and Energy-Efficient Pose Estimation in Picking Robots

• Published in: IECON 2023- 49th Annual Conference of the IEEE Industrial Electronics Society pp. 1 - 6
• Main Authors: Zhang, Teng, Yang, Minghui, Jin, Le, Zhou, Guoshun, Zhao, Xuefeng, Shi, Chao, Yuan, Xingyu, Zhou, Liang, Chang, Liang, Zhou, Jun
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16.10.2023
• Subjects: Convolutional neural networks; Energy efficiency; energy-efficient; FPGA; Industrial electronics; Iterative methods; picking robots; Pipelines; Pose estimation; pose refinement; Service robots
• ISSN: 2577-1647
• DOI: 10.1109/IECON51785.2023.10311967

Fast and energy-efficient 6D pose estimation is essential for robotic applications, especially for picking robots in industrial scene. Introducing iterative pose refinement in the final stage of pose estimation pipeline can effectively improve the precision. However, this procedure can be very time consuming due to iterative convolutional neural network (CNN) inference on resource and power constrained platforms. In this paper, we propose a FPGA-based iterative pose refinement processing unit that achieves fast and energy-efficient pose estimation for picking robots. The design and implementation are based on a Xilinx Zynq UltraScale+ MPSoC. Our experimental results demonstrate that the proposed FPGA-Based processing unit is 21.78 times faster and 23.89 times more energy-efficient compared with the baseline, significantly enhances the speed and energy efficiency of pose refinement. The evaluation result on the datasets shows little accuracy drop compared to the baseline implementation.