High Thermal Solution for 3D Integration Package

• Published in: 2023 IEEE 25th Electronics Packaging Technology Conference (EPTC) pp. 1026 - 1029
• Main Authors: Chen, Ching Chia, Kao, Nicholas, Wang, Yu Po, Lin, Shane, Li, Yung Ta
• Format: Conference Proceeding
• Language: English
• Published: IEEE 05.12.2023
• Subjects: Electromagnetic compatibility; Electronic packaging thermal management; Fans; Metals; Power system reliability; Three-dimensional displays; Through-silicon vias
• DOI: 10.1109/EPTC59621.2023.10457897

To meet request of high integration for high performance computing (HPC), package size increasing and interposer for high density interconnection are mainstream for packaging industry. As the result, large warpage and high stress are major challenges, especially scene of HPC application and advanced packaging solutions are migrating from infrastructure to PC, laptop and even automotive applications. It furtherly asks for more critical reliability requests. In addition, thermal dissipation is another challenge from high power chip. Though to attach lid on substrate is a solution to control warpage, it causes additional interfaces between package and system level dissipation module; however, metal TIM1 also causes higher stress, so need to resolve possible risks from design and material selection.FO-EB-T is a platform from SPIL which provides 3D stack-up performance and density. Fan out interposer with embedded chips provides vertical interconnection through TSV (through silicon via) which could be active, passive or bridge chips. In addition, this platform provide communication between side-by-side chips through interposer.This study applies metal TIM1on a FO-EB-T (Fan Out Embedded Chip with TSV) package between heat spreader and ASIC. The package includes a ~3.5 reticle size fan out chip module which comprises ASIC chip and multi memory on top level. Below the ASIC and memory, chips with TSV are embedded in EMC (epoxy molding compound) to provide interconnections between ASIC and memory. In addition, TSV is a shortest path between substrate and chips. Also, TMV (through mold via) in the EMC around the embedded chips are direct path for power delivery. In order to meet package warpage and reliability performance, the study includes design adjustment and material selection to balance warpage and stress.To meet target of warpage and stress criteria for such large package, low CTE substrate can reduce CTE mismatch and improve both stress and warpage. In addition, larger space between chip module and heat spreader is suggested. High thermal dissipation metal TIM2 is also used and meet TIM coverage after thermal cycle test.