Design of A Fast Transient Response Capacitor-Less LDO with Dual Loop

This paper presents a fast transient response low- dropout regulator (LDO) with enhanced slew rate and no off-chip capacitor for system-on-chip (SOC) applications. The LDO regulator uses a combination of a folded-cascode operational amplifier and a transient-enhanced circuit to drive the PMOS pass e...

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Bibliographic Details
Published in2022 10th International Symposium on Next-Generation Electronics (ISNE) pp. 1 - 3
Main Authors Wang, Ruoyang, Liou, Juin Jei, Fan, Wenbing, Wang, Yao
Format Conference Proceeding
LanguageEnglish
Published IEEE 12.05.2023
Subjects
Capacitor less LDO
Capacitors
Dual feedback loop
Fast transient response
Operational amplifiers
Regulators
Stability analysis
System-on-chip
Time factors
Transient enhanced
Transient response
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Summary:This paper presents a fast transient response low- dropout regulator (LDO) with enhanced slew rate and no off-chip capacitor for system-on-chip (SOC) applications. The LDO regulator uses a combination of a folded-cascode operational amplifier and a transient-enhanced circuit to drive the PMOS pass element. The transient enhanced circuit can improve the slew rate of power element. The introduction of a dual-loop feedback loop architecture can further improve transient response. The proposed LDO is simulated based on SK 0.1S\mum standard CMOS process. The result shows that when the input voltage is 2.1V, the output voltage is 1.SV, and the quiescent current is 37\muA. Loop stability can be maintained with a load capacitance of only 10 pF and a maximum load of 50 mA. When the load current changes from 1mA to 50mA within 10ns, the undershoot and overshoot response times are 98ps and 97ps, respectively, where the best 0.075 ps FOM is achieved.
ISSN:2378-8607
DOI:10.1109/ISNE56211.2023.10221654