A Compact Frequency Servo SoC with Background Output Power Calibration for Miniaturized Atomic Clocks

A frequency servo system-on-chip (FS-SoC) with background output power calibration technique is presented in this work for compact and ultra-low power cesium atomic clocks. With the power stabilization loop (PSL) technique, the output power of the proposed FS-SoC is stabilized to improve the accurac...

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Bibliographic Details
Published in2023 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) pp. 1 - 2
Main Authors Geng, Xinlin, Ye, Zonglin, Wang, Kailei, Zhang, Hongyang, Xie, Qian, Wang, Zheng
Format Conference Proceeding
LanguageEnglish
Published IEEE 27.10.2023
Subjects
Atomic clock
Calibration
Cesium
fractional-N PLL
Frequency servo
Phase measurement
Phase noise
Power demand
Power measurement
System-on-chip
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Summary:A frequency servo system-on-chip (FS-SoC) with background output power calibration technique is presented in this work for compact and ultra-low power cesium atomic clocks. With the power stabilization loop (PSL) technique, the output power of the proposed FS-SoC is stabilized to improve the accuracy of the atomic clocks. Manufactured in 65nm CMOS, the proposed FS-SoC is measured to achieve the phase noise performance of -69.5dBc/Hz@100Hz offset and -83.9dBc/Hz@1kHz offset respectively with a power consumption of 19.7mW. Meanwhile, the cesium (Cs) atomic clock using the proposed FS-SoC and PSL obtains an allan deviation of 1.7x10 -11 with 1-s averaging time.
ISSN:2831-3968
DOI:10.1109/ICTA60488.2023.10364271