Integrated Circuit to Compensate Parasitic Leakage Component for WL Leakage Current in NAND Flash Memory

As high-tech industries such as 5G, artificial intelligence (AI), and high-performance computers develop, the importance of processing and managing large amounts of data is increasing. Accordingly, large-capacity and high-performance products are required for VNAND Flash Memory, which records and st...

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Bibliographic Details
Published in2023 IEEE Asian Solid-State Circuits Conference (A-SSCC) pp. 1 - 3
Main Authors Nam, Bu-il, Yoon, Jayang, Lee, Kyunghea, Kim, Sol, Park, Junhong, Yoon, Chi-Weon, Kim, Eunkyoung
Format Conference Proceeding
LanguageEnglish
Published IEEE 05.11.2023
Subjects
Computers
Industries
Integrated circuits
Leakage currents
Product design
Quality assessment
Solid state circuits
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Summary:As high-tech industries such as 5G, artificial intelligence (AI), and high-performance computers develop, the importance of processing and managing large amounts of data is increasing. Accordingly, large-capacity and high-performance products are required for VNAND Flash Memory, which records and stores data. In order to satisfy these market demands, flash memory is increasing the number of layers of word lines (WL), which serve as data storage, every generation [1]-[2]. Due to the increased number of WL stacked stages to increase cell density, the space between adjacent WLs is reduced and the difficulty of the channel hole etch process is increasing. WL defects are increasing due to increased process difficulty and structural weakness. These defects cause minute leakage current on the WL and cause deterioration in product quality. In order to improve quality, electric die sorting (EDS) evaluation detects micro-leakage current on WL and screens defects, but it is difficult to accurately detect defects because it cannot reflect the influence of parasitic leakage current components of peripheral circuits. For accurate defect detection, parasitic leakage current components in the peripheral area must be removed. In this paper, we propose a new method to independently detect leakage current in the main cell area by removing parasitic components in the peripheral area that affect defect detection accuracy. In addition, Gm mismatch calibration technology is introduced to increase the accuracy of the defect detection circuit.
DOI:10.1109/A-SSCC58667.2023.10347919