Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling

This study establishes the groundwork for an industry-applicable, integrated nanosheet-based monolithic CFET process architecture with a gate pitch of 48nm. By introducing the middle dielectric isolation, inner spacer, and n/p source-drain isolation, the vertically stacked nFET-on-pFET nanosheet tra...

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Bibliographic Details
Published in2023 International Electron Devices Meeting (IEDM) pp. 1 - 4
Main Authors Liao, S., Yang, L., Chiu, T.K., You, W.X., Wu, T.Y., Yang, K.F., Woon, W.Y., Ho, W.D., Lin, Z.C., Hung, H.Y., Huang, J.C., Huang, S.T., Tsai, M.C., Yu, C.L., Chen, S.H., Hu, K.K., Shih, C.C., Chen, Y.T., Liu, C.Y., Lin, H.Y., Chung, C.T., Su, L., Chou, C.Y., Shen, Y.T., Chang, C.M., Lin, Y.T., Lin, M.Y., Lin, W.C., Chen, B.H., Hou, C.S., Lai, F., Chen, X., Wu, J., Lin, C.K., Cheng, Y.K., Lin, H.T., Ku, Y.C., Lin, S.S., Lu, L.C., Jang, S.M., Cao, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 09.12.2023
Subjects
Contacts
Logic gates
Nanoscale devices
Silicon
Stacking
Superlattices
Transistors
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Summary:This study establishes the groundwork for an industry-applicable, integrated nanosheet-based monolithic CFET process architecture with a gate pitch of 48nm. By introducing the middle dielectric isolation, inner spacer, and n/p source-drain isolation, the vertically stacked nFET-on-pFET nanosheet transistors yield a survival rate of over 90% and demonstrate high on-state current with low leakage, achieving a healthy six-order of magnitude on/off current ratio. This work sets the stage for further CFET development and paves the way for a practical process architecture that can fuel future logic technology scaling and PPAC advancement.
ISSN:2156-017X
DOI:10.1109/IEDM45741.2023.10413672