Energy-saving Processors Two-phases Frequency Reduction Algorithm on Heterogeneous Embedded Systems

• Published in: IEEE International Conference on Cyber Security and Cloud Computing (CSCloud) (Online) pp. 452 - 457
• Main Authors: Huang, Weihong, Jiang, Kuan, Huang, Jing, Lisi, Li, Xiao, Yufeng, Deng, Zihao
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2023
• Subjects: Cloud computing; directed acyclic graph; DVFS; Embedded systems; Energy consumption; Energy efficiency; Energy-saving; heterogeneous embedded systems; Scheduling; Scheduling algorithms; Time-frequency analysis
• ISSN: 2693-8928
• DOI: 10.1109/CSCloud-EdgeCom58631.2023.00083

Energy saving has become a key issue for heterogeneous embedded systems. Previous energy-saving methods attempt to minimize the energy consumption of applications in heterogeneous embedded systems subject to deadline constraints by reducing the processor frequency. However, good scheduling strategy can also minimize energy consumption to some extent. This paper proposes a novel energy-saving scheduling algorithm, called the Energy-saving Processors Two-phases Frequency Reduction (EPTFR) Algorithm. In the first stage, within the deadline constraints, the maximum working frequency of each processor is reasonably and synchronously reduced; in the second phase, when running sub-applications on the processor, under the constraints of the earliest start time and latest end time of sub-applications, the actual operating frequency of the processor is reasonably reduced. Finally, the effectiveness of the EPTFR algorithm is verified through numerical experiments, and the results show that the proposed EPTFR algorithm can achieve a significant energy-saving effect.