The Study of Slip Defects in Furnace High Temperature Process

• Published in: 2023 China Semiconductor Technology International Conference (CSTIC) pp. 1 - 7
• Main Authors: Yan, Sun, Simeng, Wei, Yuanxiang, Xie
• Format: Conference Proceeding
• Language: English
• Published: IEEE 26.06.2023
• Subjects: Costs; Furnaces; Integrated circuits; Optimization methods; Process control; Silicon; Temperature
• DOI: 10.1109/CSTIC58779.2023.10219307

As the feature size of device continues to shrink, the whole industry puts forward higher requirements for the performance and quality of silicon chips. Meanwhile, in order to reduce the cost of integrated circuit manufacturing, it has become a trend to use larger wafers (e.g. from 8 inches to 12 inches) for various silicon based devices.For those high temperature processes treated in furnace, especially exceeding 1000°C, a larger wafer size leads to an increase in thermal stress caused by gravity mostly, which often results in the defects including slip dislocations during heat treatment in high temperature oxidation and anneal processes. The dimension and distribution of slip defects are critical for devices. In some cases the aggregation and severe defects may cause device failure. Therefore, it becomes much more important to find methods to control the defect level by optimization of certain process condition to reduce the occurrence of slips during heat treatments. For instance, it is very critical for the design of wafer support structure, which is related to higher temperature requirements of vertical oxidation diffusion equipment.There are many literatures reporting on the generation and inhibition of silicon wafer slip defects. These papers mainly focus on the nailing effect of oxygen atoms, the influencing factors of gravity stress, the prediction of temperature rise and fall rate, and the theoretical calculation etc. But there are few summaries to analyze the correlations between them. Moreover, measurement techniques and early theories are needed to be updated iteratively. In this review, we describe the recent progresses in the field of silicon wafer slip and discuss the effect and following improve methods to control slip defects during various thermal processes. Meanwhile summarize the influencing factors of slip line defects, such as wafer strength, gravity-dependent stress and thermal stress, based on the formation mechanism of slip lines. Finally, we propose an optimization method to control slip defects for high-temperature process in vertical furnace.