The Study On Reducing Bit-Line Parasitic Capacitance In Advanced DRAM

In this paper, 3D TCAD (Technology Computer Aided Design) process and device simulation methods are used to explore the relationship between CBL (parasitic capacitance of bit line) and structure. The results show that BL spacer thickness and material property are critical to CBL. We suggest that BL...

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Bibliographic Details
Published in2023 China Semiconductor Technology International Conference (CSTIC) pp. 1 - 3
Main Authors Yu, Yexiao, Ma, Hong, Liu, Zhongming, Xiong, Shaoyou, Wang, Dan, Zhang, Yang, Yang, Yi
Format Conference Proceeding
LanguageEnglish
Published IEEE 26.06.2023
Subjects
Analytical models
BL profile
BL spacer
Design automation
parasitic capacitance
Random access memory
Semiconductor device modeling
Sensitivity
simulation
Solid modeling
TB ratio
TCAD
Three-dimensional displays
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Summary:In this paper, 3D TCAD (Technology Computer Aided Design) process and device simulation methods are used to explore the relationship between CBL (parasitic capacitance of bit line) and structure. The results show that BL spacer thickness and material property are critical to CBL. We suggest that BL profile should be vertical, which can give more room to BL spacer, then CBL will be reduced. Through process simulation, when BL TB ratio (top CD: bottom CD) increase from 0.6 to 0.9, the thickness of BL spacer increases by 1nm, and CBL decreases by 2. 7aF/cell.
DOI:10.1109/CSTIC58779.2023.10219287