Scaling the SOT track - A path towards maximizing efficiency in SOT-MRAM
We demonstrate, for the first time, the functionality of a scaled perpendicular spin-orbit torque (SOT)-MRAM where the SOT layer and magnetic tunnel junction (MTJ) pillar exhibit comparable dimensions. This novel design leads to a significant reduction in the power consumption (63% decrease), an enh...
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Published in | 2023 International Electron Devices Meeting (IEDM) pp. 1 - 4 |
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Main Authors | , , , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
09.12.2023
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Subjects | |
Online Access | Get full text |
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Summary: | We demonstrate, for the first time, the functionality of a scaled perpendicular spin-orbit torque (SOT)-MRAM where the SOT layer and magnetic tunnel junction (MTJ) pillar exhibit comparable dimensions. This novel design leads to a significant reduction in the power consumption (63% decrease), an enhancement in endurance (>10 15 cycles), and a reduction in bit-cell area. Systematic investigations on device scaling are performed, highlighting the importance of SOT track scaling as a path to enhance the device performance by eliminating power consumption outside the MTJ pillar region. Furthermore, the hybrid free layer stack design offers a potential solution for scaling MTJ dimensions, as it enables low switching current and sufficient retention down to 20 nm. |
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ISSN: | 2156-017X |
DOI: | 10.1109/IEDM45741.2023.10413749 |