Scaled contact length with low contact resistance in monolayer 2D channel transistors

• Published in: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
• Main Authors: Wu, Wen-Chia, Hung, Terry Y.T., Sathaiya, D. Mahaveer, Fan, Dongxu, Arutchelvan, Goutham, Hsu, Chen-Feng, Su, Sheng-Kai, Chou, Ang Sheng, Chen, Edward, Li, Weisheng, Yu, Zhihao, Qiu, Hao, Yang, Ying-Mei, Lin, Kuang-I, Shen, Yun-Yang, Chang, Wen-Hao, Liew, San Lin, Hou, Vincent, Cai, Jin, Wu, Chung-Cheng, Wu, Jeff, Philip Wong, H.-S., Wang, Xinran, Chien, Chao-Hsin, Cheng, Chao-Ching, Radu, Iuliana P.
• Format: Conference Proceeding
• Language: English
• Published: JSAP 11.06.2023
• Subjects: Contact resistance; Logic gates; Nanoscale devices; Surface resistance; Transistors; Two dimensional displays; Very large scale integration
• ISSN: 2158-9682
• DOI: 10.23919/VLSITechnologyandCir57934.2023.10185408

Two-dimensional transition metal dichalcogenides (2D TMDs) are expected to enable extremely scaled logic transistors for their ultrathin body and superior electrostatic control, i.e. gate length scaling. Aggressive scaling requires also contact length scaling. Here we demonstrate contact length scaling with low contact resistance of sub-100 Ω-μm (best data in TLM) through optimized surface preparation and semimetal/metal stack. Monolayer-MoS 2 channel transistors have the same driving current at contact length down to 30 nm. A calibrated TCAD model which captured device trends is used to extrapolate to ~250 Ω-μm at sub-15nm contact length per nanosheet of MoS 2 .