Flash ADC's low power, high speed dynamic comparator

Owing to the high conversion rate along with low power consumption, flash ADCs are the most extensively used ADCs for high frequency applications, however their precision is modest. To construct a high-speed low power flash ADC, the comparator forms the most significant block, hence it must be desig...

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Bibliographic Details
Published in2022 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering (WIECON-ECE) pp. 352 - 355
Main Authors Lakshmi, P. Vijaya, Musala, Sarada, Srinivasulu, Avireni
Format Conference Proceeding
LanguageEnglish
Published IEEE 30.12.2022
Subjects
Couplings
Delays
dynamic comparator
Flash ADC
High frequency
high speed
low power
MOS devices
Power demand
Transistors
Voltage
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Summary:Owing to the high conversion rate along with low power consumption, flash ADCs are the most extensively used ADCs for high frequency applications, however their precision is modest. To construct a high-speed low power flash ADC, the comparator forms the most significant block, hence it must be designed in such a manner that it consumes less power and has a low delay. Proposed comparator has a delay of 6.96ns and a power consumption of 6.93nW. The proposed comparator is designed utilizing cadence tool in 180nm technology with a 1.8V of supply voltage.
DOI:10.1109/WIECON-ECE57977.2022.10151081