Mitigating Inter-Chip Oscillation of paralleled SiC MOSFETs

In certain parasitic conditions, self-excited oscillation of paralleled SiC MOSFETs can occur. This kind of oscillation is known as inter-chip oscillation and can lead to loss of control, resulting in device breakdown, decreased lifetime, or significantly higher EMI. This paper reveals the mechanism...

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Bibliographic Details
Published in2023 25th European Conference on Power Electronics and Applications (EPE'23 ECCE Europe) pp. 1 - 11
Main Authors Sawallich, Florian, Eckel, Hans-Gunter
Format Conference Proceeding
LanguageEnglish
Published EPE Association 04.09.2023
Subjects
Analytical models
Damping
Design optimization
Layout
Logic gates
MOSFET
Paralleling
Semiconductor device modeling
SiC Mosfet
SiC oscillation
Silicon carbide
Stability analysis
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Summary:In certain parasitic conditions, self-excited oscillation of paralleled SiC MOSFETs can occur. This kind of oscillation is known as inter-chip oscillation and can lead to loss of control, resulting in device breakdown, decreased lifetime, or significantly higher EMI. This paper reveals the mechanism of inter-chip oscillation and presents effective methods for mitigation.
DOI:10.23919/EPE23ECCEEurope58414.2023.10264236