BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory

Three-dimensional (3D) NAND flash memory has high capacity and cell storage density by using the multi-bit technology and vertical stack architecture, but degrading data reliability due to high raw bit error rates (RBER) caused by program/erase (P/E) cycles and retention periods. Low-density parity-...

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Bibliographic Details
Published in2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 302 - 305
Main Authors Zhang, Meng, Wu, Fei, Yu, Qin, Liu, Weihua, Cui, Lanlan, Zhao, Yahui, Xie, Changsheng
Format Conference Proceeding
LanguageEnglish
Published EDAA 01.03.2020
Subjects
Computer architecture
Encoding
Error analysis
Iterative decoding
Reliability
Three-dimensional displays
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Summary:Three-dimensional (3D) NAND flash memory has high capacity and cell storage density by using the multi-bit technology and vertical stack architecture, but degrading data reliability due to high raw bit error rates (RBER) caused by program/erase (P/E) cycles and retention periods. Low-density parity-check (LDPC) codes become more popular error-correcting technologies to improve data reliability due to strong error correction capability, but introducing more decoding iterations at higher RBER. To reduce decoding iterations, this paper proposes BeLDPC: bit errors aware adaptive rate LDPC codes for 3D triple-level cell (TLC) NAND flash memory. Firstly, bit error characteristics in 3D charge trap TLC NAND flash memory are studied on a real FPGA testing platform, including asymmetric bit flipping and temporal locality of bit errors. Then, based on these characteristics, a high-efficiency LDPC code is designed. Experimental results show BeLDPC can reduce decoding iterations under different P/E cycles and retention periods.
ISSN:1558-1101
DOI:10.23919/DATE48585.2020.9116324