Benefits of Low-Power Improvements at Circuit Level on Specific FPGA Architectures

• Published in: Proceedings of IEEE International Symposium on Consumer Electronics pp. 1 - 6
• Main Authors: Niewiadomski, Karol, Tutsch, Dietmar, Pursche, Thomas
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2020
• Subjects: Costs; Current measurement; Manufacturing; Power demand; Power dissipation; Power measurement; Table lookup
• ISSN: 2158-4001
• DOI: 10.1109/ICCE46568.2020.9043139

The rising demand of computing power in mobile applications leads to the question how suitable FPGAs might be for usage in environments with limited energy resources. One of the most important benefits of FPGAs is their ability for reconfiguration and therefore adding a certain degree of flexibility in the field. In the recent years, various research groups investigated partial, dynamic reconfiguration capabilities of FPGAs and confirmed their applicability and suitability in systems with limited hardware and computing resources. However, dedicated power dissipation reduction measures are not featured by low-end designs as development and manufacturing costs take precedence over the extension of battery lifetime. In this paper, different, low-power optimized blocks are integrated into a partial slice and investigated upon the related static power consumption. Key components like LUTs, D-FFs, IO units and basic combinational circuitry are subject to power reduction and depict the baseline for further improvements in terms of extended battery runtime. These optimized blocks have been developed in past research work and enhanced by leakage current suppression measures at circuit level. The static power consumption and leakage currents of the newly implemented partial SLICE are evaluated and compared with a commercial baseline design.