Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories

We demonstrate a multi-pillar (MP) spin-orbit torque (SOT)-MRAM concept, which enables lower write current and high-density integration. We experimentally demonstrate the selective write operation of multi-bits in CMOS-compatible 300mm integrated top-pinned perpendicular MTJs. Multiple MTJs on a sha...

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Bibliographic Details
Published in2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 375 - 376
Main Authors Cai, K., Van Beek, S., Rao, S., Fan, K., Gupta, M., Nguyen, V.D., Jayakumar, G., Talmelli, G., Couet, S., Kar, G.S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 12.06.2022
Subjects
Current measurement
Logic gates
Performance evaluation
Switches
Tracking loops
Very large scale integration
Voltage measurement
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Summary:We demonstrate a multi-pillar (MP) spin-orbit torque (SOT)-MRAM concept, which enables lower write current and high-density integration. We experimentally demonstrate the selective write operation of multi-bits in CMOS-compatible 300mm integrated top-pinned perpendicular MTJs. Multiple MTJs on a shared SOT track can be individually selected by gate voltages and independently switched by sub-ns pulses with 30% reduction in operation current. Our concept of selective operations with less transistors and lower writing energy will significantly enhance the density and energy efficiency of SOT-MRAM.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46769.2022.9830307