Design Space Exploration of a Reconfigurable Accelerator in a Heterogeneous Multicore

• Published in: 2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI) pp. 1 - 6
• Main Authors: Silva, Francisco Carlos, Patrocinio, Joao P. dos S., Silva, Ivan Saraiva, Jacobi, Ricardo Pezzuol
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2020
• Subjects: Computer science; Hardware; Multicore processing; Out of order; Performance evaluation; Space exploration
• DOI: 10.1109/SBCCI50935.2020.9189915

Energy-efficiency has become one of the most important characteristics in system design, especially in mobile devices. However, keeping the energy-efficiency while maintaining the performance in applications with different demand profiles is challenging. In order to meet the distinct application's requirement, single-ISA heterogeneous multicore systems have been proposed, such as ARM's big.LITTLE. Despite these systems offer different micro-architectural cores to meet the application's demands, only a fixed number of core types are available, limiting the system adaptability. Coarse-Grained Reconfigurable Architectures (CGRA) are highly programmable accelerators and have been successfully used to provide run-time adaptability in single-core systems. This work proposes to integrate ATHENA, a transparent CGRA, to a heterogeneous multicore system in order to improve the system adaptability. A design space exploration is carried out, by changing the number of functional units available in ATHENA, to evaluate distinct energy-performance tradeoffs. Additionally, the area costs introduced by ATHENA are also evaluated. The results show that the most energy-efficient version of ATHENA improves the performance of a low-energy core in 35% while consuming 21.90% less energy, on average, introducing only 13.68% of area overhead. The ATHENA also improves the performance of the high-performance core in 42%, on average, than the standalone high-performance core.