29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur

• Published in: 2021 IEEE International Solid- State Circuits Conference (ISSCC) Vol. 64; pp. 410 - 412
• Main Authors: Zhang, Qiaochu, Su, Shiyu, Ho, Cheng-Ru, Chen, Mike Shuo-Wei
• Format: Conference Proceeding
• Language: English
• Published: IEEE 13.02.2021
• Subjects: Calibration; Clocks; Jitter; Phase noise; Ring oscillators; Solid state circuits; Tuning
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC42613.2021.9365819

Ring oscillator (RO)-based frequency synthesizers enable cost-efficient and scaling-friendly implementation, but also result in worse phase noise compared to LC-based alternatives. There has been increasing interest in injecting a low-noise reference clock signal to the RO to refresh the accumulated jitter, as seen in multiplying delay-locked loops (MDLLs) and injection-locked phase-locked loops (IL-PLLs). The main challenge of this architecture is that the injection signal derived from the reference clock is not perfectly aligned with the RO phase at the injection node, hence spurious tones are generated, and this phase alignment issue is especially exacerbated in fractional-N operation as the injection time paint must gradually drift away from the reference clock phase [1]. One way of achieving this required phase drift is by tuning digital-to-time converters (DTCs) according to a fractional frequency multiplication ratio; however, DTC offset and gain errors can introduce spurs. Several works have demonstrated DTC calibration, but are either limited to foreground calibration or incur an additional time-to-digital converter (TDC) [2], [3]. To further suppress injection-locking-induced spurs, we propose a background DTC calibration scheme that: 1) simultaneously estimates DTC gain and offset errors by occasional injection squelching; 2) performs two-point gain and offset error correction in the respective analog and digital domains; 3) uses TDC dithering [4] to enhance error estimation accuracy; and 4) removes dithering noise with an adaptive comb-filter-assisted cancellation loop. To prove the concept, a fractional-N digital MDLL using the DTC calibration scheme is implemented in 65nm CMOS and demonstrates 1.67ps RMS jitter and -60dBc fractional spur with 26dB spur suppression.