Noise Margin Calculation in Multiple-Valued Logic

Noise margin (NM) is an important concept in circuit design since noise is one of the major challenges for reliability. This subject is very critical in multiple-valued logic (MVL), where the entire voltage range is divided into several narrow zones. Ternary NMs are currently calculated based on a c...

Full description

Saved in:
Bibliographic Details
Published inInternational eConference on Computer and Knowledge Engineering (Online) pp. 250 - 255
Main Authors Takbiri, Mehdi, Navi, Keivan, Mirzaee, Reza Faghih
Format Conference Proceeding
LanguageEnglish
Published IEEE 29.10.2020
Subjects
Inverter
Inverters
Mathematical model
Multiple-Valued Logic
Multivalued logic
Noise Margin
Quaternary Logic
Resistance
Simulation
Ternary Logic
Transistors
Visualization
Online AccessGet full text
ISSN2643-279X
DOI10.1109/ICCKE50421.2020.9303638

Cover

More Information
Summary:Noise margin (NM) is an important concept in circuit design since noise is one of the major challenges for reliability. This subject is very critical in multiple-valued logic (MVL), where the entire voltage range is divided into several narrow zones. Ternary NMs are currently calculated based on a conventional definition. In this paper, we use another slightly different definition to present a new set of equations. Our investigations show that the proposed equations are more accurate and return closer results to reality. Furthermore, the given explanations are extended beyond ternary logic in this paper for MVL NM calculations in higher radixes.
ISSN:2643-279X
DOI:10.1109/ICCKE50421.2020.9303638