Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm

• Published in: 2019 IEEE International Electron Devices Meeting (IEDM) pp. 19.1.1 - 19.1.4
• Main Authors: Prasad, Divya, Teja Nibhanupudi, S. S., Das, Shidhartha, Zografos, Odysseas, Chehab, Bilal, Sarkar, Satadru, Baert, Rogier, Robinson, Alex, Gupta, Anshul, Spessot, Alessio, Debacker, Peter, Verkest, Diederik, Kulkarni, Jaydeep, Cline, Brian, Sinha, Saurabh
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2019
• ISSN: 2156-017X
• DOI: 10.1109/IEDM19573.2019.8993617

The technology of buried power rails and back-side power delivery has been proposed for future scaling enablement, beyond the 5nm technology node. This paper studies the CPU design implications of power delivery in the context of these technologies. Employing standard VLSI design flows and sign-off techniques, we benchmark the power delivery designs and technology options using the Arm Cortex-A53 CPU at an imec 3nm technology node. DC and AC analyses of the resulting power delivery networks are presented for the various designs with buried power rails (with front-side and back-side power delivery) and compared to conventional designs without buried power rails. It is shown that buried rails with front-side power delivery can improve the worst-case IR drop from 70mV to 42mV (~1.7X reduction) while buried rails with back-side power delivery substantially reduce IR drop to 10mV (a 7X reduction).