Constructing Effective UVM Testbench By Using DRAM Memory Controllers

• Published in: 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS) pp. 1034 - 1038
• Main Authors: Kabilan, R., Ravi, R., Esther, J. Monica, Muthuraman, U., Gabriel, J. Zahariya, Devaraj, G. Prince
• Format: Conference Proceeding
• Language: English
• Published: IEEE 23.02.2022
• Subjects: Codes; IP networks; Memory architecture; Random access memory; Robustness; SoC; TEST BENCH; UVM; Very large scale integration; Visualization
• DOI: 10.1109/ICAIS53314.2022.9742986

A basic testing architecture to DRAM memory controllers is given in this paper. The suggested verification architecture based upon universal verification methodology, it employs common characteristics among numerous DRAM memory controllers that offer an standardized test-cases, UVM components, scoreboard and payload. The verification architecture provided employs the fewest possible macros, methods, and classes. UVM tests can be reused thanks to the proposed verification architecture. SoC Verification has been one of the greatest subjects in VLSI. The verification process requires well over 70% of the total time. As a result, a reusable and resilient verification environment is required. The universal verification methodology, is a viable solution to such issues. In a few simple stages, it also teaches how to validate an IP and build up an efficient verification environment. In a SoC case study, traditional verification is matched with UVM-based verification.