A feasible scheduling algorithm for per-VC queueing ATM switches

This paper introduces a scheduling algorithm for per-VC queueing ATM switches. Our proposed per-VC queueing scheduler (PVQS) achieves a low maximum delay, provides bandwidth guarantee, and fairly allocates excess capacity. The computation in PVQS is carried out on a per-connection basis, not on a pe...

Full description

Saved in:
Bibliographic Details
Published in1999 2nd International Conference on ATM. ICATM'99 (Cat. No.99EX284) pp. 295 - 304
Main Authors Peifang Zhou, Yang, O.W.W.
Format Conference Proceeding
LanguageEnglish
Published Piscataway NJ IEEE 1999
Subjects
Applied sciences
Asynchronous transfer mode
Clocks
Exact sciences and technology
Information technology
Processor scheduling
Quality of service
Scheduling algorithm
Switches
Systems, networks and services of telecommunications
Telecommunications
Telecommunications and information theory
Teleprocessing networks. Isdn
Teletraffic
Tellurium
Traffic control
Virtual colonoscopy
Queueing system
Telecommunication network
Theoretical study
Traffic control
Scheduling
Service quality
Switching system
Asynchronous transmission
Online AccessGet full text

Cover

More Information
Summary:This paper introduces a scheduling algorithm for per-VC queueing ATM switches. Our proposed per-VC queueing scheduler (PVQS) achieves a low maximum delay, provides bandwidth guarantee, and fairly allocates excess capacity. The computation in PVQS is carried out on a per-connection basis, not on a per-cell basis which is mandatory in the virtual time-stamp type of approach. This leads to a significant reduction in computational effort and makes PVQS a feasible candidate for practical implementation in per-VC queueing ATM switches.
ISBN:9780780354289
0780354281
DOI:10.1109/ICATM.1999.786815