Performance Analysis of Various FINFET Threshold Logic based Full Adder Design

• Published in: 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) pp. 1 - 5
• Main Authors: Sarkar, Mili, Nasir, Shagufta Talaat, Chakraborty, Indrani, Maity, Sougata, Chakraborty, Ribhu, Taki, G.S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2019
• Subjects: B driven Threshold Logic; CMOS; COWL(Capacitive output wired Logic) insert; FINFET; Threshold Logic
• DOI: 10.1109/IEMENTech48150.2019.8981275

Full adder is the basic building block of all computing systems. Various Full adder circuits have been presented here, which are uniquely designed using FINFET based Threshold Logic gates. These Full Adders consist of Ganged/ output wired FINFET based Inverter, Capacitive output wired logic (COWL) and Beta-driven threshold logic circuits. The designed circuits are compared on several important parameters e.g., time delay, power consumed by an unit cell and the number of transistor used in a cell. Here FINFET based simulations have been carried using LTSPICE for 45nm and 32nm technology. Some interesting properties have been observed in the simulations. Capacitive output wired logic based full adder cell shows the best performance with respect to transistor count, delay, average power and power delay product.