A 7nm 0.46pJ/bit 20Gbps with BER 1E-25 Die-to-Die Link Using Minimum Intrinsic Auto Alignment and Noise-Immunity Encode

This work presents a high-density low bit error rate and low-power Mlink (MediaTek link) PHY for ultra-short-reach (USR) die-to-die communication. Proposed Mlink have been fabricated in TSMC 7nm FinFET 1P15M CMOS technology. Interconnection is demonstrated through TSMC Chip-on-Wafer-on-Substrate (Co...

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Bibliographic Details
Published in2021 Symposium on VLSI Circuits pp. 1 - 2
Main Authors Hsu, Ying-Yu, Kuo, Po-Chun, Chuang, Chih-Lun, Chang, Po-Hao, Shen, Hung-Hao, Chiang, Chen-Feng
Format Conference Proceeding
LanguageEnglish
Published JSAP 13.06.2021
Subjects
Bandwidth
Bit error rate
chip-to-chip
CoWoS
DCDL
de-skew
die-to-die
encode
Energy efficiency
FinFETs
InFO
interposer
Mlink
Packaging
seamless
SI/PI
USR
Very large scale integration
Wires
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Summary:This work presents a high-density low bit error rate and low-power Mlink (MediaTek link) PHY for ultra-short-reach (USR) die-to-die communication. Proposed Mlink have been fabricated in TSMC 7nm FinFET 1P15M CMOS technology. Interconnection is demonstrated through TSMC Chip-on-Wafer-on-Substrate (CoWoS) and TSMC Integrated Fan-Out (InFO) packaging technology [1]. Mlink PHY exploits energy-efficient and high performance scheme, includes single-ended without termination, quarter rate strobe and unbalance scheme on transceiver, minimum intrinsic auto-alignment and novel noise-immunity coding methodology. Achieving 20Gb/s/wire and 0.46pJ/bit under 1-mm ultra-short-reach platform target to BER 1E-25. Bandwidth density is normalized with shoreline 5.31Tb/s/mm and area 2.25Tb/s/mm^2 respectively.
ISSN:2158-5636
DOI:10.23919/VLSICircuits52068.2021.9492439