Design Validation of Recurrent Signal Processor FPGA prototype

This paper describes the final stage of the FPGA prototype development of a recurrent signal processor. During the development of this prototype, a set of tools was created, based on which design verification was carried out. We describe the development process and the prototype validation methodolo...

Full description

Saved in:
Bibliographic Details
Published in2021 IEEE East-West Design & Test Symposium (EWDTS) pp. 1 - 5
Main Authors Stepchenkov, Yury, Khilko, Dmitry, Shikunov, Yury, Orlov, Georgy
Format Conference Proceeding
LanguageEnglish
Published IEEE 10.09.2021
Subjects
Computer architecture
Data models
data-flow
design validation
digital signal processing
Prototypes
Registers
Software
VHDL
Online AccessGet full text

Cover

More Information
Summary:This paper describes the final stage of the FPGA prototype development of a recurrent signal processor. During the development of this prototype, a set of tools was created, based on which design verification was carried out. We describe the development process and the prototype validation methodology on a class of DSP tasks using a demo task of isolated word recognition. Taking the previously developed tools and methods for verifying software and hardware models, we have developed a specialized design validation tool. This solution made it possible to ensure the uniformity of the validation process for various types of architecture implementation and to establish the correctness of their operation.
ISSN:2472-761X
DOI:10.1109/EWDTS52692.2021.9581005