Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route

• Published in: 2019 International 3D Systems Integration Conference (3DIC) pp. 1 - 4
• Main Authors: Sisto, Giuliano, Debacker, Peter, Chen, Rongmei, Van Der Plas, Geert, Chou, Richard, Beyne, Eric, Milojevic, Dragomir
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2019
• Subjects: Logic gates; Metals; Three-dimensional displays; Timing; Two dimensional displays
• DOI: 10.1109/3DIC48104.2019.9058901

We present extensions to commercially available EDA tools to support Wafer-to-Wafer (W2W), Face-to-Face (F2F), hybrid bonding 3D integration with ~1μm pitch Cupad structures. Proposed flow is based on Innovus™ Place & Route (P&R) tool from Cadence Design Systems and allows functional 3D system partitioning with user specified partitioning information and automated netlist split. Due to fine 3D pitch, the partitioning can occur at lower levels of system hierarchy, resulting in significant number of 3D pins and with die-crossing critical paths. Proposed flow has been validated using memory-on-logic split of a single OpenSPARC-T2 core. L1 memory macros have been extracted from the post-synthesized gate-level netlist using a dedicated automated netlist partitioner. Per die netlists and top-level system have been fed into the P&R flow, memory die being implemented first. 3D structures have been assigned to 3D nets automatically, allowing their optimal placement with respect to the memory macros pins. 3D pin positions of the memory die have been propagated as a constraint for the implementation of the logic die, allowing optimized standard cell placement with respect to the 3D pins. Finally, we have enabled a cross-die timing analysis to assess the improvements of 3D in comparison to 2D. Our results show up to 40% of the total wirelength savings and 25 % on the maximum one, resulting in a 19% timing improvement on critical path.