Statistical circuit characterization for deep-submicron CMOS designs

Aggressive scaling of CMOS MOSFET gate lengths is halving minimum device channel lengths every 4 to 6 years. This brings an increase in deep-submicron device performance sensitivity to manufacturing variations. Its impact on highly-integrated, system-on-a-chip designs needs assessment to ensure firs...

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Bibliographic Details
Published in1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) pp. 90 - 91
Main Authors Chen, J., Orshansky, M., Chenming Hu, Wan, C.-P.
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 1998
Subjects
Analytical models
Circuit optimization
CMOS logic circuits
Principal component analysis
Ring oscillators
Semiconductor device modeling
SPICE
Stochastic systems
Threshold voltage
Velocity measurement
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Summary:Aggressive scaling of CMOS MOSFET gate lengths is halving minimum device channel lengths every 4 to 6 years. This brings an increase in deep-submicron device performance sensitivity to manufacturing variations. Its impact on highly-integrated, system-on-a-chip designs needs assessment to ensure first-pass silicon and adequate yield.
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ISBN:9780780343443
0780343441
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.1998.672388