Area-Time Scalable High Radix Montgomery Modular Multiplier for Large Modulus

• Published in: 2021 25th International Symposium on VLSI Design and Test (VDAT) pp. 1 - 4
• Main Authors: Kolagatla, Venkata Reddy, Desalphine, Vivian, Selvakumar, David
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16.09.2021
• Subjects: Adders; Carry Save Adder; Carry Select Adder; Combinational circuits; Field programmable gate arrays; Hardware; High Radix/Digit Serial Multipliers; Measurement; Montgomery Modular Multiplier; Security; Very large scale integration
• DOI: 10.1109/VDAT53777.2021.9601001

Adoption of large modulus and field sizes for RSA and ECC are of the norm for meeting present day's security requirements and goals. Modular multiplication (MM) is the key computational unit for both and requires large hardware resources (area) and incurs huge latency. Typically, Montgomery Modular Multiplier and Interleaved Modular Multiplier are being adopted for RSA and ECC respectively for designing efficient hardware. Lower Area-time (AT) product is the key design metric to consider both latency (time to compute one MM) and area together as a combined metric. Combinational circuit to compute partial products of a particular modulus for higher radices increases area and critical path, reduces frequency, and latency. Here, the increase in area dominates the reduction in latency with respect to radix, resulting in an increased AT metric for the given modulus. This work presents a table look up technique for the multiplication factors which is used to compute partial products of modulus in MR-MMM (Multi-Radix Montgomery Modular Multiplier). This approach reduces the AT metrics with increasing radices for a given larger modulus enabling an AT scalable hardware and has been proven on Virtex 7 and 6 FPGAs for modulus 256 to 4096 with radices 2 to 2 12 .