2x2 Matrix Multiplication with 4-Bit elements in 45nm CMOS Technology

• Published in: 2020 4th International Conference on Electronics, Communication and Aerospace Technology (ICECA) pp. 69 - 75
• Main Authors: Patel, Chiranjit R, Urankar, Vivek, A, Vivek B, R, Sampath Kumar
• Format: Conference Proceeding
• Language: English
• Published: IEEE 05.11.2020
• Subjects: Adders; CMOS; Computer architecture; Conferences; Layout; Matrix multiplier; Power demand; Random access memory; SRAM; Urdhva Tiryagbhyam; Vedic - multiplier
• DOI: 10.1109/ICECA49313.2020.9297489

A simple and effective method for matrices multiplication is proposed. The determination of the resultant output matrix can either performed in parallel or sequentially, both resulting in the same output. The selection of the algorithm is application-specific and filters down to the frequency of operation or power consumption. Multipliers and adders are the main hardware blocks in a matrix multiplication system. Hence, choosing a multiplier which is not only fast but also consumes lesser power and area is vital. This study also proposes a modified 2-bit and 4-bit multiplier architectures based on Vedic mathematics, which is proven to be more efficient than the standard architectures. The simulations are performed using Cadence Virtuoso 45nm CMOS technology. The proposed 7T SRAM cell makes use separate write and reads ports which are controlled by Read Word Line (RWL) and Write Word Line (WWL). Specter simulations are performed for voltage ranges from 0.8V to 1.5V. The simulations also show that the matrix multiplier of 2-bit and 4-bit elements can operate at 2GHz and 0.7GHz at 1.2V respectively, and consumes an average of 140\muW and 350\muW. The layouts designed in 45nm are found to be matching with the schematic (LVS clean) and follows all Foundry rules (DRC clean).