A 20 MB/s data rate 2.5 V flash memory with current-controlled field erasing for 1 M cycle endurance
Techniques to improve endurance and access time are applied to 2.5V high-density flash memory. A 4Mb flash product is used as a test vehicle for an erase method that extends the program/erase (P/E) endurance beyond 106 cycles. An embedded /spl mu/ROM controller with optimized algorithms (zero P/E ar...
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Published in | 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers Vol. 40; pp. 396 - 397 |
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Main Authors | , , , , , , , , , , , , |
Format | Conference Proceeding Journal Article |
Language | English |
Published |
IEEE
01.01.1997
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Subjects | |
Online Access | Get full text |
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Summary: | Techniques to improve endurance and access time are applied to 2.5V high-density flash memory. A 4Mb flash product is used as a test vehicle for an erase method that extends the program/erase (P/E) endurance beyond 106 cycles. An embedded /spl mu/ROM controller with optimized algorithms (zero P/E array stress) minimizes erase time (parallel sector erase) and reduces testing time (BIST techniques). A 20MB/s read data throughput at 2.5V is obtained in OE synchronized data transfer mode. Dynamic redundancy enhances repair capability. |
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Bibliography: | SourceType-Scholarly Journals-2 ObjectType-Feature-2 ObjectType-Conference Paper-1 content type line 23 SourceType-Conference Papers & Proceedings-1 ObjectType-Article-3 |
ISBN: | 9780780337213 0780337212 |
ISSN: | 0193-6530 2376-8606 |
DOI: | 10.1109/ISSCC.1997.585456 |