A high precision 1024-point FFT processor for 2D convolution

• Published in: 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) pp. 118 - 119
• Main Authors: Wosnitza, M., Cavadini, M., Thaler, M., Troster, G.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 1998
• Subjects: Convolution
• ISBN: 9780780343443; 0780343441
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.1998.672398

A chip for real-time computation of 256-, 512- and 1024-point Fourier-transforms uses architecture targeting frequency-domain convolution of real-valued 1024/spl times/1024 data-sets at 5 Frames/s. Compared to existing FFT-designs, the processor also supports element-wise matrix multiplication (MUL) and dedicated pre- and post-processing steps required for simultaneous transformation of two real-valued sequences with one complex FFT (cf. real-valued FFT). In addition, considering the large dynamic numerical range required for 2D frequency-domain convolution, the ALU-arithmetic is based on twos complement data-sets represented with 64b (2/spl times/32) complex mantissa and an additional 8b exponent. Under nominal conditions of 20/spl deg/C room temperature and 3.3 V power supply, the ALU computes a complex 1024-pt FFT within 80 /spl mu/s.