Connection Resource Testing Technology on FPGA Based on SOC core

For FPGA testing, usually hundreds of code streams need to be loaded. Because SoC FPGA is embedded with processor system, its code stream loading method is very different from traditional FPGA. This article provides a configuration code selection interface for ATE by designing a startup program, and...

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Bibliographic Details
Published in2021 IEEE 15th International Conference on Electronic Measurement & Instruments (ICEMI) pp. 383 - 390
Main Authors Xie, Weikun, Nan, Ziyuan, Gao, Shi
Format Conference Proceeding
LanguageEnglish
Published IEEE 29.10.2021
Subjects
Codes
configuration
Field programmable gate arrays
FPGA
Instruments
interconnection
Loading
SOPC
Testing
Wiring
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Summary:For FPGA testing, usually hundreds of code streams need to be loaded. Because SoC FPGA is embedded with processor system, its code stream loading method is very different from traditional FPGA. This article provides a configuration code selection interface for ATE by designing a startup program, and makes PS reconfigure PL according to the user's choice, and load a different configuration code for each test. The deterministic wiring test method can fully cover the FPGA wiring resources. This paper proposes a deterministic wiring method based on Zynq-7000 series chips to traverse the wiring resources of the SoC FPGA and generate configuration codes. Finally, the wiring resource test of SoC FPGA is realized through ATE and the above code stream loading scheme.
DOI:10.1109/ICEMI52946.2021.9679613