Pre-Synthesis Evaluation of Digital Bus Micro-Architectures

Buses are central building blocks in the architecture of digital systems. There are numerous standards for bus architectures and evaluation metrics in terms of data transfer rate, quality of service, and latency; however, it is not common to find metrics related to the physical features of bus imple...

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Bibliographic Details
Published in2020 IEEE 3rd Conference on PhD Research in Microelectronics and Electronics in Latin America (PRIME-LA) pp. 1 - 4
Main Authors Garcia-Ramirez, R., Chacon-Rodriguez, A., Strydis, C., Rimolo-Donadio, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.02.2020
Subjects
Bus
Clocks
Interconnects
Micro-Architecture
Power demand
Protocols
Routing
Synchronization
System-on-Chip
Throughput
Very Large Scale Integration
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Summary:Buses are central building blocks in the architecture of digital systems. There are numerous standards for bus architectures and evaluation metrics in terms of data transfer rate, quality of service, and latency; however, it is not common to find metrics related to the physical features of bus implementations, such as power consumption and area in terms of their microarchitecture. This paper evaluate bus micro-architectures at pre-synthesis level, allowing for the comparison of alternative circuits implementing the same standard and thus providing estimations on the power consumption and area requirements. A metric is proposed to evaluate the bus implementation and its utilization is shown with generic serial and parallel buses, based on simulations with a 0.18µm CMOS standard cell library.
DOI:10.1109/PRIME-LA47693.2020.9062719