Contour Based Solution For Identifying Mask Induced Error

• Published in: 2021 International Workshop on Advanced Patterning Solutions (IWAPS) pp. 1 - 3
• Main Authors: Yu, Yinsheng, Liu, Guoping, Zhao, Hongwen, Zhou, Kan, Li, Yuhui, Zhou, Wenzhan, Zhang, Yu, Wan, Qijian, Chen, Ao, Du, Chunshan, Zhang, Liguo, Fenger, Germain
• Format: Conference Proceeding
• Language: English
• Published: IEEE 12.12.2021
• Subjects: Conferences; Feeds; Foundries; Hot spot; Industries; Inspection; Lithography; Mask; Process Window; Semiconductor device modeling
• DOI: 10.1109/IWAPS54037.2021.9671258

The Lithography is the key process for the semi-conductor foundry industry, consists of a bunch of factors such as: OPC error, exposure tool error, and mask error et al. Mask-related issue, as a key factor affecting process window, which is very difficult to identify by conventional method [1]. Furthermore, mask inspection and measurement consumes large resource to find out the relationship between mask and wafer. In this paper, we propose a new solution by using contour-based to figure out the mask to wafer error. Which could find the print down error between different version mask manufacture issue or mask to mask bias that is corresponding on wafer process window. This solution used mask SEM images and AIMS (Aerial Image Measurement System) data contour extraction overlay the wafer CDSEM results. The final PV band calculation results could define mask error, OPC model error, and identify a total solution to feedback or even feed forward to mask shop or OPC site. This method could discover the mask induced problems before mask in and could save Fab resource to check pattern performance