A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET

This paper describes the design of a 1.24pJ/b 112Gb/s PAM4 transceiver testchip in 7nm FinFET for in-package die-to-die communication. The receiver supports 0-1.2V input common mode and utilizes a single-stage active inductor-based CMOS CTLE with 12 data slicers and 2 error slicers. The quad-rate vo...

Full description

Saved in:
Bibliographic Details
Published in2021 Symposium on VLSI Circuits pp. 1 - 2
Main Authors Poon, Chi Fung, Zhang, Wenfeng, Cho, Junho, Ma, Shaojun, Wang, Yipeng, Cao, Ying, Laraba, Asma, Ho, Eugene, Lin, Winson, Wu, Daniel, Tan, Kee Hian, Upadhyaya, Parag, Frans, Yohan
Format Conference Proceeding
LanguageEnglish
Published JSAP 13.06.2021
Subjects
Delays
Feeds
FinFETs
Receivers
Transceivers
Transmitters
Very large scale integration
Online AccessGet full text

Cover

More Information
Summary:This paper describes the design of a 1.24pJ/b 112Gb/s PAM4 transceiver testchip in 7nm FinFET for in-package die-to-die communication. The receiver supports 0-1.2V input common mode and utilizes a single-stage active inductor-based CMOS CTLE with 12 data slicers and 2 error slicers. The quad-rate voltage-mode transmitter implements delay based sub-UI two-tap FFE and digital I/Q and DCC clock calibration. A single-phase clock from a wideband LC PLL is distributed to eight transceiver channels. In each channel, an ILO generates eight-phase clocks that feed an 8-bit CMOS PI. The transceiver achieves <1e-12 BER over 30mm channel @106.25Gb/s and over 20mm channel @112Gb/s.
ISSN:2158-5636
DOI:10.23919/VLSICircuits52068.2021.9492467