A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus

• Published in: 2022 IEEE International Solid- State Circuits Conference (ISSCC) Vol. 65; pp. 446 - 448
• Main Authors: Lee, Daewoong, Kwon, Hye-Jung, Kwon, Daehyun, Baek, Jaehyeok, Cho, Chulhee, Kim, Sanghoon, An, Donggun, Chang, Chulsoon, Lim, Unhak, Im, Jiyeon, Sung, Wonju, Kim, Hye-Ran, Park, Sun-Young, Kim, HyoungJoo, Seol, Hoseok, Kim, Juhwan, Shin, Junabum, Kang, Kil-Youna, Kim, Yona-Hun, Kim, Sooyoung, Park, Wansoo, Kim, Seok-Jung, Lee, Chanyong, Lee, Seungseob, Park, TaeHoon, Oh, ChiSung, Ban, Hyodong, Ko, Hyungjong, Song, Hoyoung, Oh, Tae-Young, Hwang, SangJoon, Oh, Kyung Suk, Choi, JungHwan, Lee, Jooyoung
• Format: Conference Proceeding
• Language: English
• Published: IEEE 20.02.2022
• Subjects: Conferences; Graphics; Power supplies; Random access memory; Time-frequency analysis; Training; Voltage
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC42614.2022.9731614

Graphic DRAMs have been developed to increase maximum I/O interface speeds to satisfy the demand of high-performance graphic applications [1]-[5]. Recently, PAM4 signaling was utilized to increase the I/O bandwidth up to 22Gb/s/pin [5]. However, the reduced voltage margin of PAM4, compared to NRZ, complicates circuit design; margins also become worse with a reduced power supply. This paper achieves 27Gb/s in NRZ, a 1.5× speed enhancement, by improving on previous GDDR6 [3]. A T-coil is designed, for the first time in a DRAM process, so that the maximum operation frequency is increased. The proposed merged-MUX TX increases the maximum speed and reduces power and area consumption. A quad-skew training technique enables a wider clock sampling margin for WCK: up to 3ps, which is 8.1% of 1UI at 27Gbp/s/pin. Furthermore, a dual-mode frequency divider allows a wide-range operation from sub-1Gb/s/pin to 27Gb/s/pin. An alternative-data-bus (ADB) is proposed to solve the frequency limit of the data bus.