Pipelined extended-counting ${\bf I\Delta \Sigma}$IΔΣ for 3D-stacked CMOS image sensors

• Published in: Electronics letters Vol. 56; no. 23; pp. 1239 - 1241
• Main Authors: Callens, N, Lefebvre, J, Gielen, G
• Format: Journal Article
• Language: English
• Published: The Institution of Engineering and Technology 12.11.2020
• Subjects: 3D‐stacked CMOS image sensors; 3D‐stacked imagers; analogue‐digital conversion; chopped images; Circuits and systems; CMOS image sensors; discontinuous rolling shutter artefacts; EC principle; high frame rate; novel multistage pipelined extended‐counting IΔΣ; pipelined ADC; temperature 8.0 K; three‐dimensional integrated circuits; chopped images; temperature 8.0 K; 3D-stacked imagers; CMOS image sensors; I; high frame rate; analogue-digital conversion; pipelined ADC; novel multistage pipelined extended-counting IΔΣ; 3D-stacked CMOS image sensors; EC principle; three-dimensional integrated circuits; discontinuous rolling shutter artefacts
• ISSN: 0013-5194; 1350-911X; 1350-911X
• DOI: 10.1049/el.2020.2030

A novel multi-stage pipelined extended-counting (EC) ${\rm I}\Delta \Sigma $IΔΣ for 3D-stacked CMOS image sensors is presented, which combines the benefits of a pipelined ADC, a first-order ${\rm I}\Delta \Sigma $IΔΣ ADC and the EC principle in order to simultaneously achieve a high resolution and a high frame rate for 3D-stacked imagers. By assigning each stage of the pipeline to a sub-column of pixels while choosing another input stage of the pipeline when a sub-column has been read out, discontinuous rolling shutter artefacts like chopped images can be eliminated and frame rates up to 340 fps can be achieved for imagers with 8 K resolution.