3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

• Published in: IEEE journal of solid-state circuits pp. 1 - 9
• Main Authors: Osada, Yoshiaki, Nakazato, Takaaki, Aoyagi, Yumito, Nii, Koji, Liaw, Jhon-Jhy, Wu, Shien-Yang, Li, Quincy, Fujiwara, Hidehiro, Liao, Hung-Jen, Chang, Tsung-Yung Jonathan
• Format: Journal Article
• Language: English
• Published: IEEE 19.08.2024
• Subjects: Cache family; Circuits; Decoding; FinFET; FinFETs; Logic; MOS devices; Random access memory; row decoder leakage saving (RDLS); static random-access memory (SRAM); Transistors; write driver leakage saving
• ISSN: 0018-9200
• DOI: 10.1109/JSSC.2024.3440970

Row decoder leakage saving (RDLS) and high-speed write driver leakage saving (HS-WDLS) circuits are proposed to reduce leakage power while keeping high access speed. The proposed circuits achieve a 71% reduction in leakage power. Additionally, a detailed discussion on the trade-off between switching current increase and leakage current reduction is presented. The overhead of switching power is 0.3% and 1.9% for read and write operations, respectively. Simulation results show that our static random-access memory (SRAM) has actual power reduction when active rate is lower than 21% at 25 <inline-formula> <tex-math notation="LaTeX">^{\circ}</tex-math> </inline-formula>C, 81% at 75 <inline-formula> <tex-math notation="LaTeX">^{\circ}</tex-math> </inline-formula>C, and 100% at 85 <inline-formula> <tex-math notation="LaTeX">^{\circ}</tex-math> </inline-formula>C or higher. Silicon measurements demonstrate that it operates at a frequency of 3.7 GHz at 1.4 V and has a wide-range operation down to 0.5 V. It achieves the best figure of merit (FoM), defined as density <inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> <inline-formula> <tex-math notation="LaTeX">F_{\mathrm{max}}</tex-math> </inline-formula>.