An analytical approach to hardware-friendly adaptive learning rate neural networks

In this paper hardware implementation of adaptive learning rate neural networks is studied. Some design guidelines are presented to improve integration of learning algorithm into the hardware. By using them, it is possible to design high performance neural networks, which are capable of handling a r...

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Published inProceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004 pp. 320 - 323
Main Authors Ghannad Rezaie, M., Farbiz, F., Fakhraie, S.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2004
Subjects
Adaptive systems
Algorithm design and analysis
Circuits
Computer networks
Convergence
Learning systems
Network-on-a-chip
Neural network hardware
Neural networks
Neurons
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Summary:In this paper hardware implementation of adaptive learning rate neural networks is studied. Some design guidelines are presented to improve integration of learning algorithm into the hardware. By using them, it is possible to design high performance neural networks, which are capable of handling a rapidly-conversing learning algorithm in analog chips. The analytical approach developed in this work provides more insight towards tuning of a reliable design. Our experimental results prove that this approach performs above the conventional fixed learning rate approach, and is almost comparable to the ideal gradient based adaptive approach.
ISBN:0780386566
9780780386563
DOI:10.1109/ICM.2004.1434278