Embedded ferroelectric memory using a 130-nm 5 metal layer Cu / FSG logic process

An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu / FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was...

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Bibliographic Details
Published inProceedings. 2004 IEEE Computational Systems Bioinformatics Conference pp. 153 - 154
Main Authors Summerfelt, S., Aggarwal, S., Boku, K., Celii, F., Hall, L., Matz, L., Martin, S., McAdams, H., Remack, K., Rodriguez, J., Taylor, K., Udayakumar, K.R., Moise, T., Bailey, R., Depner, M., Fox, G., Eliason, J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2004
Subjects
Capacitors
Chemical vapor deposition
Degradation
Fabrication
Ferroelectric films
Ferroelectric materials
Logic
MOCVD
Nonvolatile memory
Random access memory
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Summary:An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu / FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The bit distribution of small ferroelectric capacitors (< 0.2 /spl mu/m/sup 2/) was measured after fabrication and bake. A reasonable amount of property degradation after 6000hr 125/spl deg/C bake was observed.
ISBN:9780780387263
0780387260
DOI:10.1109/NVMT.2004.1380833