Current mirror test structures for studying adjacent layout effects on systematic transistor mismatch

This paper discusses a new current mirror based test structure that is used to identify and quantify systematic transistor mismatch degradation associated with layout features close to high precision current mirror transistors.

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Bibliographic Details
Published inInternational Conference on Microelectronic Test Structures, 2003 pp. 221 - 226
Main Authors Tuinhout, H.P., Bretveld, A., Peters, W.C.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2003
Subjects
Circuit testing
Consumer electronics
Electronic equipment testing
Measurement standards
Mirrors
MOSFETs
Semiconductor device testing
Signal processing
System testing
Transistors
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Summary:This paper discusses a new current mirror based test structure that is used to identify and quantify systematic transistor mismatch degradation associated with layout features close to high precision current mirror transistors.
ISBN:0780376536
9780780376533
DOI:10.1109/ICMTS.2003.1197465